Windows中的Sysinternals套件的Coreinfo工具查看NUMA
Tags： CoreinfoNUMAOSSysinternalsWindows
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简介
Coreinfo 是一个命令行实用工具，用于显示逻辑处理器与物理处理器、NUMA 节点和套接字之间的映射，以及分配给每个逻辑处理器的缓存。 它使用 Windows 的 GetLogicalProcessorInformation 函数获取此信息并将其打印到屏幕，表示与带有星号的逻辑处理器（例如“*”）的映射。 Coreinfo 可用于深入了解系统的处理器和缓存拓扑。
安装
将存档提取到目录，然后通过键入 32 位 Windows 版本或 Coreinfo64 64 位版本的控制台中的该目录Coreinfo来运行 Coreinfo。
使用 CoreInfo
对于每个资源，它显示与指定资源对应的 OS 可见处理器的映射，其中“*”表示适用的处理器。 例如，在 4 核系统上，缓存输出中的一行与核心 3 和 4 共享的映射。
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用法：coreinfo [-c][-f][-g][-l][-n][-s][-m][-v]
| 参数 | 说明 |
|---|---|
| -c | 有关核心的转储信息。 |
| -f | 转储核心功能信息。 |
| -g | 有关组的转储信息。 |
| -l | 有关缓存的转储信息。 |
| -n | NUMA 节点上的转储信息。 |
| -s | 有关套接字的转储信息。 |
| -m | 转储 NUMA 访问成本。 |
| -v | 仅转储与虚拟化相关的功能，包括支持二级地址转换。 |
| (需要 Intel 系统上的管理权限) 。 |
默认情况下，除 -v 之外的所有选项均处于选中状态。
Coreinfo 输出：
shell复制
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 | Coreinfo v3.03 - Dump information on system CPU and memory topology Copyright (C) 2008-2011 Mark Russinovich Sysinternals - www.sysinternals.com Intel(R) Xeon(R) CPU W3520 @ 2.67GHz Intel64 Family 6 Model 26 Stepping 5, GenuineIntel EM64T * Supports 64-bit mode VMX - Supports Intel hardware-assisted virtualization SVM - Supports AMD hardware-assisted virtualization HYPERVISOR * Hypervisor is present HTT * Supports hyper-threading SMX - Supports Intel trusted execution SKINIT - Supports AMD SKINIT EIST * Supports Enhanced Intel Speedstep NX * Supports no-execute page protection PAGE1GB - Supports 1GB large pages PAE * Supports > 32-bit physical addresses PAT * Supports Page Attribute Table PSE * Supports 4-MB pages PSE36 * Supports > 32-bit address 4-MB pages PGE * Supports global bit in page tables SS * Supports bus snooping for cache operations VME * Supports Virtual-8086 mode FPU * Implements i387 FP instructions MMX * Supports MMX instruction set MMXEXT - Implements AMD MMX extensions 3DNOW - Supports 3DNow! instructions 3DNOWEXT - Supports 3DNow! extension instructions SSE * Supports Streaming SIMD Extensions SSE2 * Supports Streaming SIMD Extensions 2 SSE3 * Supports Streaming SIMD Extensions 3 SSSE3 * Supports Supplemental SIMD Extensions 3 SSE4.1 * Supports Streaming SIMD Extensions 4.1 SSE4.2 * Supports Streaming SIMD Extensions 4.2 AES - Supports AES extensions AVX - Supports AVX intruction extensions FMA - Supports FMA extensions using YMM state MSR * Implements RDMSR/WRMSR instructions MTTR * Supports Mmeory Type Range Registers XSAVE - Supports XSAVE/XRSTOR instructions OSXSAVE - Supports XSETBV/XGETBV instructions CMOV * Supports CMOVcc instruction CLFSH * Supports CLFLUSH instruction CX8 * Supports compare and exchange 8-byte instructions CX16 * Supports CMPXCHG16B instruction DCA - Supports prefetch from memory-mapped device F16C - Supports half-precision instruction FXSR * Supports FXSAVE/FXSTOR instructions FFXSR - Supports optimized FXSAVE/FSRSTOR instruction MONITOR - Supports MONITOR and MWAIT instructions MOVBE - Supports MOVBE instruction PCLULDQ - Supports PCLMULDQ instruction POPCNT * Supports POPCNT instruction SEP * Supports fast system call instructions DE * Supports I/O breakpoints including CR4.DE DTES64 - Can write history of 64-bit branch addresses DS - Implements memory-resident debug buffer DS-CPL - Supports Debug Store feature with CPL PCID - Supports PCIDs and settable CR4.PCIDE PDCM - Supports Performance Capabilities MSR RDTSCP * Supports RDTSCP instruction TSC * Supports RDTSC instruction TSC-DEADLINE - Local APIC supports one-shot deadline timer xTPR * Supports disabling task priority messages ACPI * Implements MSR for power management TM * Implements thermal monitor circuitry TM2 * Implements Thermal Monitor 2 control APIC * Implements software-accessible local APIC x2APIC - Supports x2APIC CNXT-ID - L1 data cache mode adaptive or BIOS MCE * Supports Machine Check, INT18 and CR4.MCE MCA * Implements Machine Check Architecture PBE * Supports use of FERR#/PBE# pin PSN - Implements 96-bit processor serial number Logical to Physical Processor Map: *--- Physical Processor 0 -*-- Physical Processor 1 --*- Physical Processor 2 ---* Physical Processor 3 Logical Processor to Socket Map: **** Socket 0 Logical Processor to NUMA Node Map: **** NUMA Node 0 Logical Processor to Cache Map: *--- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64 *--- Instruction Cache 0, Level 1, 32 KB, Assoc 4, LineSize 64 *--- Unified Cache 0, Level 2, 256 KB, Assoc 8, LineSize 64 -*-- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64 -*-- Instruction Cache 1, Level 1, 32 KB, Assoc 4, LineSize 64 -*-- Unified Cache 1, Level 2, 256 KB, Assoc 8, LineSize 64 --*- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64 --*- Instruction Cache 2, Level 1, 32 KB, Assoc 4, LineSize 64 --*- Unified Cache 2, Level 2, 256 KB, Assoc 8, LineSize 64 ---* Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64 ---* Instruction Cache 3, Level 1, 32 KB, Assoc 4, LineSize 64 ---* Unified Cache 3, Level 2, 256 KB, Assoc 8, LineSize 64 **** Unified Cache 4, Level 3, 8 MB, Assoc 16, LineSize 64 Logical Processor to Group Map: **** Group 0 |
